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3-A DC Motor Driver
TLE 5203
Overview Features * * * * * * * * Output current 3 A I/O error diagnostics Short-circuit proof Four-quadrant operation Integrated free-wheeling diodes Wide temperature range Open load detection Break low, if break high required, the device TLE 5204 will fit
SPT IC 1)
P-TO220-7-1
P-TO220-7-8 Type TLE 5203 TLE 5203 G Description TLE 5203 is an integrated power bridge with DMOS output stages for driving DC motors. This motor bridge is optimized for driving DC motors in reversible operation. The internal protective circuitry in particular ensures that no crossover currents can occur. Because the free-wheeling diodes are integrated, the external circuitry that is necessary is reduced to the capacitors on the supply voltage. The control inputs have TTL/CMOS-compatible levels.
1)
Ordering Code Q67000-A9096 Q67006-A9242
Package P-TO220-7-1 P-TO220-7-8
SIEMENS Power Technology
Semiconductor Group
1
1998-02-01
TLE 5203
TLE 5203
TLE 5203 G
1
2
345
6
7
EF Q1 1
GND 2
VS
Q2
AEP01224
Figure 1
Pin Configuration (top view)
Semiconductor Group
2
1998-02-01
TLE 5203
Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 Symbol Q1 EF I1 GND I2 Function Output of channel 1; Short-circuit proof, free-wheeling diodes integrated for inductive loads Error flag; TTL/CMOS-compatible output for error detection (open drain) Control input 1; TTL/CMOS-compatible Ground; connected internally to cooling fin Control input 2; TTL/CMOS-compatible Supply voltage; wire with capacitor matching load Output of channel 2; Short-circuit proof, free-wheeling diodes integrated for inductive loads
VS
Q2
Circuit Description Input Circuit The control inputs consist of TTL/CMOS-compatible Schmitt triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. Output Stages The output stages form a switched H-bridge. Protective circuits make the outputs shortcircuit proof to ground and to the supply voltage throughout the operating range. Positive and negative voltage spikes, which occur when switching inductive loads, are clamped by integrated power diodes.
Semiconductor Group
3
1998-02-01
TLE 5203
Functional Truth Table E1 L L H H E2 L H L H Q1 H L L Z Q2 L H L Z Comments Motor turns counterclockwise Motor turns clockwise Brake; both low side transistors turned-ON Open circuit detection
Notes for Output Stage Symbol L H Z Value Low side transistor is turned-ON High side transistor is turned-OFF High side transistor is turned-ON Low side transistor is turned-OFF High side transistor is turned-OFF Low side transistor is turned-OFF
Monitoring Functions An internal circuit ensures that all output transistors are turned-OFF if the supply voltage is below the operating range. A monitoring circuit for each output transistor detects whether the particular transistor is active and in this case prevents the corresponding source transistor (sink transistor) from conducting in sink operation (source operation). Therefore no crossover currents can occur. Pulse-width operation is possible up to a maximum switching frequency of 1 kHz for any load. Depending on the load current higher frequencies are possible. Protective Function Various errors like short-circuit to + VS, ground or across the load are detected. All faults result in turn-OFF of the output stages after a delay of 40 s and setting of the error flag EF to ground. Changing the inputs resets the error flag. Output Shorted to Ground Detection If a high side transistor is switched on and its output is shorted to ground, the output current is limited to typ 8 A. After a delay of 40 s all outputs will be switched off and the error flag EF is set to ground.
Semiconductor Group
4
1998-02-01
TLE 5203
Output Shorted to + VS and Overload Detection An internal circuit detects if the current through the low side transistor is higher than 4 A typ. In this case all outputs are turned off after 40 s and the error flag EF is set to ground. At a junction temperature higher than 160 C the thermal shutdown turns off, all four output stages commonly and the error flag is set without a delay. Open Load Detection The output Q1 has a 10 k pull-up resistor and the output Q2 has a 10 k pull-down resistor. If E1 and E2 are high, all output power stages are turned-OFF. In case of no load between Q1 and Q2 the output voltage Q1 is VS and Q2 is ground. This state will be detected by two comparators and an error flag will be set after a delay time of 40 s. Changing the inputs resets the error flip flop. Diagnosis Input E1 L L H H E2 L H L H Output Q1 H L L Z Q2 L H L Z Shorted to GND Q1 Q2 - - Diagnosis Shorted to VS Q2 Q1 Q1, Q2 - Overload X X - - Open Load - - - X L L L L EF
Semiconductor Group
5
1998-02-01
TLE 5203
V EH =
Pull Up 10 k EF Pull Down 10 k
= V EL
&
40 s
RS FF
AES01688
Figure 2
Simplified Schematic for Open Load Detection
Error Flag 2 Error Flag Protection Circuit 1
VS
6
Control Input 1
3
1
Output 1
Control Input 2
5
7
Output 2
Protection Circuit 1
4 GND
AEB01225
Figure 3
Block Diagram
Semiconductor Group
6
1998-02-01
TLE 5203
Absolute Maximum Ratings Tj = - 40 to 150 C Parameter Symbol Limit Values min. Voltage Supply voltage Supply voltage Logic input voltage Diagnostics output voltage Current Free-wheeling current Output current 1) Junction temperature Storage temperature Thermal Resistance Junction-case Junction-ambient Operating Range Supply voltage Logic input voltage Switching frequency 2) Junction temperature
1)
Unit
Remarks
max.
VS VS VI1 , 2 VEF
- 0.3 -1 - 0.3 - 0.3
40 - 7 7
V V V V
-
t < 500 ms; IS < 5 A VS = 0 - 40 V
-
IF IQ Tj Tstg
-4 -4 - 40 - 50
4 4 150 150
A A C C
Tj 150 C
- - -
Rth jC Rth jA
- -
4 65
K/W K/W
- -
VS VI1 , 2 f Tj
6 - 0.3 - - 40
24 7 1 150
V V kHz C
- - - -
During overload condition currents higher than 4 A can dynamically occur, before the device shuts off, without any damaging the device. Depending on load higher frequencies are possible.
2)
Semiconductor Group
7
1998-02-01
TLE 5203
Electrical Characteristics VS = 6 to 18 V; Tj = - 40 to 150 C Parameter Symbol Limit Values min. General Quiescent current Turn-ON delay Turn-OFF delay Turn-ON time Turn-OFF time Undervoltage Undervoltage Logic Control inputs H-input voltage L-input voltage Hysteresis of input voltage H-input current L-input current Diagnosis output Delay time L-output voltage Leakage current Error detection Switching threshold U Switching threshold L Overcurrent 1 typ. max. Unit Test Condition
Iq td1 td2 tr tf VS VS
- - - - - - -
- 10 - 10 - 5.5 4.5
10 20 10 20 10 5.9 5.2
mA s s s s V V
IL = 0 A
Input to output Input to output IQ = 2.5 A; cf diagram IQ = 2.5 A; cf diagram
IC ON IC OFF
VIH VIL
VI
2.8 - 0.4 -2 - 10 20 - - 2 2 3
- - 0.8 - -4 40 - - 2.7 2.7 4
- 1.2 1.2 2 0 60 0.4 10 3.5 3.5 5
V V V A A s V A V V A
- - -
II II td VEF IRD VEH VEL IF1
VI = VIH VI = VIL
-
I = 3 mA
- Error low Error high Error low
Semiconductor Group
8
1998-02-01
TLE 5203
Electrical Characteristics (cont'd) VS = 6 to 18 V; Tj = - 40 to 150 C Parameter Symbol Limit Values min. Outputs RDSONU RDSONU RDSONL RDSONL Diode forward voltage Diode forward voltage Pull up/pull down
1)
Unit
Test Condition
typ.
max.
- - - -
VFU VFL R
- - - - - - 5
- - - - - - 10
0.4 0.65 0.4 0.65 1.5 1.5 25
V V k
VS > 6 V; Tj = 25 C 1) VS > 6 V; Tj = 150 C 1) VS > 6 V; Tj = 25 C 1) VS > 6 V; Tj = 150 C 1) IF = 3 A IF = 3 A
-
Values for RDSON are for t > 100 s after applying + VS.
Semiconductor Group
9
1998-02-01
TLE 5203
q, S
4700 F 63V
470nF
6
2 1
VS
1
3
Q1
RL VEF
TLE 5203
V 1
2
5 4
7
Q2
V 2
M
VQ2
V Q1
AES01226
Figure 4
Test Circuit
Figure 5
Timing Diagram
10 1998-02-01
Semiconductor Group
TLE 5203
+ VS = 12 V 220 nF
*)
5V 2 k Error Flag 2 3 Control Inputs 5 4
AES01228
6 1
TLE 5203
7
M
*) Necessary for isolating supply voltage or interruption (e.g. 470 F).
Figure 6
Application Circuit
Semiconductor Group
11
1998-02-01
TLE 5203
Diagrams
RON Resistance of Output Stage over Temperature
800
AED01305
Output Voltage on Diagnostics Output versus Current
300
AED01306
R ON
m 600
6 V< VS <18 V
VEF
mV 250
max
200
VS =12 V
T j = 150 C
typ 400
150
T j = 25 C
100
200
50
0
0
25
50
75
100
C
150
0
0
1
2
3
4
mA
6
Tj
Forward Current of Upper Free-Wheeling Diode versus Voltage
F
4 A 3
AED01303
Forward Current of Lower Free-Wheeling Diode versus Voltage
F
4 A 3
AED01304
T j = 150 C T j = 25 C
2
2
T j = 150 C T j = 25 C
1
1
0 0.2
0.6
1
V
1.4
0 0.2
0.6
1
V
1.4
VF
VF
Semiconductor Group
12
1998-02-01
TLE 5203
Overcurrent Threshold versus Temperature
10
AED01681
Quiescent Current versus Temperature
5
AED01682
Q
A 8 typ 6 min
S
mA 4
3
typ
4
2
2
1
0 -40
0
40
80
120 C 160
0 -40
0
40
80
120 C 160
Tj
Tj
Input Threshold versus Temperature
3.5
AED01683
Switching Threshold VEL, EH versus Temperature
5.5
AED01684
V
V 3.0
VF
V 5.0
2.5
typ
V H
4.5 typ
2.0 typ 1.5
4.0
V L
3.5
1.0 -40
0
40
80
120 C 160
3.0 -40
0
40
80
120 C 160
Tj
Tj
Semiconductor Group
13
1998-02-01
TLE 5203
E2 8A
E1 = Low
Q2
V Q2
R Short x 8 A
40 s
V FL
EF
AED01685
Figure 7
Timing Diagram for Output Shorted to Ground
E2 20 A
E1 = Low
Q1
VS V Q1 R Short x 20 A
40 s EF
AED01686
V FU
Figure 8
Timing Diagram for Output Shorted to VS
14 1998-02-01
Semiconductor Group
TLE 5203
E2
E1 = Low
Overcurrent Switching Threshold
F1
Load
40 s
VS
VF
V Q1 R ON x Load VS R ON x Load V Q2
VF
EF
AED01687
Figure 9
Timing Diagram for Overcurrent
15 1998-02-01
Semiconductor Group
TLE 5203
Normal Mode E1
Open Circuit
E2
VS V Q1 V S /2
V Q2
40 s EF
AED01691
Figure 10 Timing Diagram for Open Load
Semiconductor Group
16
1998-02-01
TLE 5203
Package Outlines P-TO220-7-1 (Plastic Transistor Single Outline)
10 +0.4 10.2 -0.2 3.75
+0.1
4.6 -0.2 1 x 45 1.27
+0.1
2.8
19.5 max
16 0.4
8.8 -0.2
2.6 0.4 +0.1 8.4 0.4
8.6 0.3
15.4 0.3
GPT05108
1 1.27
7 0.6 +0.1
1)
0.6 M 7x
4.5 0.4
1) 0.75 -0.15 at dam bar (max 1.8 from body) 1) 0.75 -0.15 im Dichtstegbereich (max 1.8 vom Korper)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Semiconductor Group 17
10.2 0.3
Dimensions in mm 1998-02-01
TLE 5203
P-TO220-7-8 (SMD) (Plastic Transistor Single Outline)
4.6 1.27 10.2 8.0 1)
3.5
0.2 2.6
10.1
0.6 1.27 6 x 1.27 = 7.62
0.4
GPT05874
1) shear and punch direction burr free surface
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 18
1.5
8.8
Dimensions in mm 1998-02-01

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